The abstract of Japanese Patent Application Publication Laid-Open No. 2005-79129 (Patent Document 1) discloses a plastic package 10 including first extension lines 18 short-circuiting a plurality of second conductor wiring patterns 17a not connected to a plating extension line 16, a tie-line 19 connecting the first extension lines 18 with each other, and a first conductor wiring pattern 17 connected to the plating extension line 16 via a second extension line 18a. In a state that the first conductor wiring pattern 17 is connected to the tie-line 19, electroplating is performed to form an electroplating film 15 on the second conductor wiring patterns 17a via the first conductor wiring pattern 17. Following the formation of the electroplating film 15, the tie-line 19 is eliminated at an eliminating portion 21 to disconnect the second conductor wiring patterns 17a from each other.
The paragraphs [0010] and [0012] of Japanese Patent Application Publication Laid-Open No. 2014-82299 (Patent Document 2) disclose a configuration in which, in order to prevent the cracking of a semiconductor chip that happens when an etch-back trench (equivalent to “eliminating portion 21” of Patent Document 1) crosses the semiconductor chip, the etch-back trench crossing the semiconductor chip is divided into separate trenches in an inner area of the semiconductor chip.